1. Field of the Invention
The present invention relates to a display driving system, and more particularly, to a display driving system using single level data transmission with embedded clock signals, which is configured to embed a clock signal of the same level between data signals and transmit these signals as a single level signal, wherein a cycle at which clock signals are embedded is controlled and a data format is constructed such that a control data transmission step can be extended over 2 words.
2. Description of the Related Art
These days, as the digital home appliance market is grown and the distribution of personal computers and portable communication terminals is increased, display devices as final output devices of home appliances and communication terminals are required to be light in weight and consume a small amount of power. Techniques for meeting these requirements are continuously proposed in the art. Accordingly, flat display devices, such as an LCD (liquid crystal display), a PDP (plasma display panel) and an OELD (organic electro-luminescence display), which replace the conventional CRT (cathode ray tube), have been developed and are being distributed.
Each of the flat display devices includes a timing controller which processes RGB data and generates a timing control signal so as to drive a panel used for displaying received RGB data, and column driving units and row driving units which drive the panel using the RGB data and the timing control signal transmitted from the timing controller.
In particular, recently, differential signal transmission schemes capable of reducing electromagnetic interference (EMI) and transmitting data at a high speed, such as mini-LVDS (low voltage differential signaling) and RSDS (reduced swing differential signaling), have been increasingly used.
FIG. 1 is a view illustrating transmission of data differential signals and clock differential signals in conventional LVDS, and FIG. 2 is a view illustrating transmission of data differential signals and clock differential signals in conventional RSDS.
Referring to FIGS. 1 and 2, the recently used mini-LVDS or RSDS has at least one data differential signal line which is connected to a timing controller 10 so as to support a desired bandwidth and a separate clock differential signal line which is configured to output a clock differential signal in synchronism with a data differential signal, and adopts a multi-drop scheme in which respective column driving units 20 share the data differential signal line and the clock differential signal line.
While the multi-drop scheme has advantages in that the timing controller 10 can be used irrespective of the number of outputs depending upon a resolution, that is, the number of the column driving units 20, it encounters a problem in that signal distortion by reflection waves is caused and electromagnetic interference (EMI) increases due to impedance mismatch occurring at points where the data differential signal and the clock differential signal are supplied to the respective column driving units 20, and in that an operation speed is limited due to a large load applied to the clock differential signal.
In order to overcome the problem caused in the multi-drop scheme, PPDS (point-to-point differential signaling), in which data differential signals are separately supplied to respective column driving units and a clock differential signal is shared by the column driving units, has been proposed in the art.
FIG. 3 is a view illustrating transmission of data differential signals through independent data signal lines in conventional PPDS, and FIG. 4 is a view illustrating chain type transmission of clock differential signals in another conventional PPDS.
Referring to FIG. 3, in PPDS, an independent data line is formed between a timing controller 10 and each column driving unit 20 so that data differential signals are separately supplied to respective column driving units 20. Therefore, impedance mismatch, electromagnetic interference (EMI) and overloading of a clock differential signal that can otherwise be caused in the multi-drop scheme can be overcome.
In the PPDS, the clock differential signal should be transmitted at a high speed. In this regard, because the PPDS shown in FIG. 3 is configured to share the clock differential signal, an operation speed is limited when a load applied to the clock differential signal is substantial. Hence, as shown in FIG. 4, a signal transmission scheme is used, in which a clock differential signal is supplied to the respective column driving units 20 in a chain type. In this case, a problem is caused in that sampling of data is not properly implemented due to clock delay occurring between the column driving units 20.
Further, as display devices trend toward a large screen size and a high resolution and the number of column driving units increases accordingly, the PPDS scheme encounters a problem in that the numbers of data and clock signal lines increase at the same rate, connection of entire signal lines is complicated, and a high manufacturing cost results.
FIG. 5 is a view illustrating a conventional AiPi (advanced intra-panel interface).
Referring to FIG. 5, the AiPi has recently been suggested in which data and clock signals are distinguished by multi-levels and data differential signals with clock signals embedded therebetween are transmitted from a timing controller to column driving units through independent respective signal lines. Therefore, the number of signal lines can be significantly decreased, and electromagnetic interference (EMI) is reduced. Also, since the operation speed and the resolution of a panel are increased despite the decrease in the number of signal lines, it is possible to solve the problems caused by skew or jitter occurring between the data and clock signals while transmitting signals at a high speed.
In the recently proposed AiPi transmission scheme, while signals are transmitted by embedding clock signals between data to decrease the number of signal lines and prevent the occurrence of skew between the data and clock signals, since the embedded clock signals are transmitted to constitute multi-level signals by having a level higher or lower than data signals, problems are caused in that it is impossible to minimize the level of signals to be transmitted and reduction of electromagnetic interference (EMI) is poor.
As a consequence, an interface for transmitting data at a high speed between a timing controller and column driving units, which can decrease the number of signal lines for transmitting data differential signals and clock differential signals, minimize electromagnetic interference (EMI), and prevent the occurrence of skew and jitter between signal lines, is keenly demanded in the art.
In order to meet the demand, the present applicant has disclosed a display driving system using single level signaling with embedded clock signals in Korean Patent Application No. 2008-102492 filed on Oct. 20, 2008, wherein a clock signal of the same level is embedded between data signals in a timing controller and is transmitted through an independent data signal line to each panel driving unit in the type of a single level signal, and the clock signal is recovered in the panel driving unit, data is sampled and RGB data is outputted to a panel, so that a data transmission speed can be maximized and the level of signals to be transmitted and the frequency of the embedded clock signal can be minimized.
However, while a cycle at which a clock signal is embedded is associated with RGB data, influence by internal interference increases as the bit depth of the RGB data or a transmission rate increases, by which the jitter of an input signal increases. As a consequence, it becomes difficult to compare the phase of a clock signal which is recovered by a clock recovery circuit of a data receiving section and the phase of a clock signal which is embedded in data.
In a control data transmission period (a configuration period) between a clock training period and a data period, control data corresponding to a maximum RGB data size can be transmitted. In this regard, in the case where the cycle at which the clock signal is embedded is smaller than the data size or the control data larger than the data size should be transmitted, limitations exist in implementing configuration.